Programmable integrated circuits (ICs) are often used to implement digital logic operations according to user configurable input. Example programmable ICs include complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs often include several function blocks that are based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transmits signals between the function blocks.
One type of FPGA includes an array of programmable tiles. The programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth. Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
A conventional design process for programmable ICs begins with the creation of the design. The design is then compiled for implementation in a particular programmable IC device. During compilation, a circuit design can be “synthesized” to produce a representation of the circuit design in terms of specific logic elements, which can be optimized to the architecture of the programmable IC (e.g., lookup tables (LUTs), carry logic, 10 buffers, etc.). To generate an optimal implementation in terms of area in the programmable IC, the synthesis process can attempt to combine some logic elements together, including specific pairs of logic elements. Methods currently used to combine or “pack” pairs of logic elements during circuit design employ greedy algorithms. Greedy algorithms can be fast, but can also produce suboptimal results. Generally, greedy algorithms do not reconsider previous packing choices to improve the overall result. Suboptimal packing of logic element pairs results in suboptimal implementation area for the circuit design and suboptimal usage of resources in the programmable IC.